| Position: | Senior FPGA Developer / Team Lead |
| Location: | Vancouver, BC Canada |
| Employment: | Full-Time |
Obsidian is a dynamic technology company developing high-performance optical communications equipment that interfaces to compute clusters and supercomputers. The company's Longbow technology addresses military, enterprise, science/ simulation and higher education markets, where speed, correctness and reliability are paramount.
You will be part of a tightly-integrated multi-disciplinary team focused on developing 10 to 100 gigabit networking equipment with a focus on InfiniBand and line rate stream data processing.
Your duties will likely include but are not limited to:
- Digital system architecture and design
- Oversight of junior developers
- FPGA development using VHDL and Synplicity
- Verification using object oriented, constrained random test techniques in System Verilog
- Build automation, scripting, and configuration management
- Work with the software and PCB teams to collect, establish and verify digital design requirements
- High level part selection and vetting
- Oversight of in-circuit digital validation
The successful candidate will have the following skills:
- Strong understanding of the VHDL language and use of VHDL with Synplify for FPGA synthesis
- Thorough understanding of Xilinx Virtex 4 and 5 hardware architectures
- Experience with object-oriented and other programming methodologies, including past design work in C++, Java or Python or strong existing experience with System Verilog for verification
- Ability to work effectively in a Linux based development environment
- Excellent troubleshooting skills
- Past successful FPGA or ASIC designs (5 or more years recent relevant industry work experience)
A strong preference will be given to candidates that possess the following skills or knowledge:
- System Verilog and OVM
- SV DPI (in C++), SVA and PSL
- QuestaSim (or ModelSim)
- GNU make, bash, TCL, python, git and other tools
- InfiniBand protocol, physical, electrical, and link
- 1G/10G/40G Ethernet protocol, including RGMII, SGMII, XAUI, XSBI and CTBI
- SONET/SDH (broadly)
- IPv4 and IPv6 protocol stacks
- Ethernet MAC-SEC, AES and GCM
- Various common interfaces: DDR, DDR2, QDR2, SPI4.2, SFI4.1
- Xilinx hard IP blocks, including all flavours of GTs
- Theory of successful high speed design - signal integrity, power integrity, jitter and other physical analog effects
- C++
The successful candidate will be exposed to all of the above and will be expected to learn on the job as necessary.
Candidates with the following education are preferred:
- Degree in Computer Science, Electrical or Computer Engineering
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